1. Technical Field
The present invention relates to device testing in general, and in particular, to a method and apparatus for performing logic built-in self-testing of an integrated circuit.
2. Description of Related Art
One of the problems with semiconductor test techniques is associated with the usage of automatic test equipment (ATE) to apply the test patterns at the device's external inputs and measure the responses at the device's external outputs. This approach does not provide a means to adequately detect all of the device's internal defects. Direct access to the internal structures of a device is necessary. This need has led to the development of design-for-test (DFT) and logic built-in self-test (LBIST) techniques and methods.
DFT techniques include design rules and constraints aimed at increasing the testability of a design through increased internal test controllability and observability. A well-known form of DFT is level sensitive scan design (LSSD), which involves modifying the internal storage elements of a device such that, in a test mode, the storage elements form individual stages of a shift register for scanning in test data stimuli and scanning out test responses.
The LBIST approach was developed from the fact that much of the electronics of a circuit tester is semiconductor-based, just like the products that are being tested. Since many limitations in ATE-based testing are a consequence of the interface to the device-under-test, the LBIST approach moves many of the test equipment functions (which are already semiconductor-based) into the products-under-test to eliminate the complex interfacing.
Logic built-in self-test (LBIST) is used for manufacturing test at all package levels and for system self-test. An LBIST implementation generates test vectors to detect potential faults in the device-under-test while the output responses are measured at the primary outputs. LBIST adds a pseudo-random pattern generator (PRPG) to the inputs and a multiple-input shift register (MISR) to the outputs of the device's internal storage elements, which are arranged to form the scan chains disclosed above. Pseudo-random patterns are applied to the logic-under-test by scanning the pseudo-random pattern into STUMPS channels (known as channel fill) and executing a test sequence that consists of scan and functional clock cycles. An LBIST controller generates all necessary waveforms for repeatedly loading pseudorandom patterns into the scan chains, initiating a functional cycle, and logging the captured responses out into the MISR. The MISR compresses the accumulated responses into a code known as a signature. Any corruption in the final signature at the end of the test indicates a defect in the chip.
The DFT logic supporting LBIST tests (LBIST DFT logic) of a device-under-test may have a fault just like any other logic of the device. During manufacturing test, the LBIST DFT logic is used to test the functional logic of the device-under-test. Therefore, it is essential that the LBIST DFT logic is operational prior to any LSSD test application protocols or the test will fail. In the prior art, LBIST DFT logic is not tested prior to LSSD test application protocols. As a result, when a device-under-test fails, a tester does not know if the LBIST DFT logic or the functional logic of the device-under-test is faulty. Furthermore, if the LBIST DFT logic was faulty, then performing the LSSD test application protocols is unnecessary. Given the dramatic increase in density of VLSI devices and overall market trends for 3D integration and systems-on-a-chip, eliminating unnecessary LSSD tests would result in significant test time reduction.